The field of threshold logic is gaining prominence as an alternative to Boolean logic as a result of an increase in the availability of devices that implement threshold logic circuits efficiently, for example, current mode circuits and/or differential mode circuits. One of the many advantages of threshold logic is that logic primitives may be replaced by elements of a much larger class of functions known as threshold logic gates. For instance, each of the Boolean functions ab(c+d)+cd(a+b) and a(b+c+d)+b(c+d)+cd, may be realized by a single threshold logic gate. If a Boolean function may be realized as a network of threshold logic gates, significantly fewer nodes and a smaller network depth may be required.
There have been numerous efficient implementations of threshold logic gates in CMOS that have achieved high performance and significantly reduced area. CMOS circuits implementing Boolean logic may have higher functional yield in the presence of process variations, when compared to threshold logic circuits. A plurality of nano devices, for example, resonant tunneling diodes (RTDs), single electron transistors (SETs), quantum-dot cellular automata (QCA) cells and other nano devices have been implementing threshold logic circuits, and accordingly there is a need in the design automation community to design efficient tools for threshold logic.
The synthesis of a circuit may comprise transforming one representation of a function to another, usually to a more detailed specification. The process equivalence checking (EC) may be related to synthesis, and may entail demonstrating an equivalence of two functional representations. The function of a synthesized circuit may be verified with a given functional specification. In addition, engineering changes that may be introduced throughout a design process may introduce errors in the synthesized circuit. Demonstrating equivalence may also be required between two different representations of the same circuit generated at different phases in the design flow.
The naive way to determine the logic function of a threshold gate may be to try all 2n input combinations and determine the on-set of the function, and generate a sum-of-products (SOP) representation. One of the features of threshold gates is that they permit efficient realization (both in area and delay) of gates with large fan-in. Hence the naive approach may not be practical.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.